The present invention relates generally to the fabrication of semiconductor devices, and more specifically to forming self-aligned contacts to the field-effect transistors (FETs) having replacement metal gates.
FETs are commonly employed in electronic circuit applications. FETs may include a semiconductor substrate containing a source region and a drain region spaced apart by a channel region. A gate, potentially including a gate dielectric layer, a work function metal layer, and a metal electrode, may be formed above the channel region. In part to protect the gate, insulating spacers may be formed on the side of the gate. By applying voltage to the gate, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region.
Due in part to the relative instability of the dielectric layer and work function metal layer of the gate, a gate-last process may be used where a sacrificial gate is formed prior to forming other components of the FET. The sacrificial gate may then be removed to form a recessed region that may then be filled with a replacement metal gate (RMG) potentially including a gate dielectric layer, a work function metal layer, and a metal electrode. Because the RMG is formed after the other components of the FET, it is not subjected to various potentially damaging processing steps, for example high-temperature anneals.
To allow current to flow to and from the source and the drain region, respectively, electrical contacts may be formed on the source region and the drain region. The contacts may be formed by etching contact holes in the dielectric layer. As transistor structures continue to become smaller in size, it becomes increasingly difficult to lithographically define the borders of the contact holes. As a result, techniques have been developed to use the insulating spacers to form borderless, self-aligned contacts (SAC). Borderless contacts may be formed so that there is no remaining material of the dielectric layer between the contact and the spacers. By using the spacers to define the contact, it may be possible to maximize the interface between the contact and the source/drain region while also utilizing a less precise lithographic process.
However, in order to incorporate both a RMG and a SAC into a FET, it may be necessary to protect the RMG with an insulating cap to prevent short-circuiting between the RMG and the SAC. In some cases, this may be accomplished by recessing the RMG after its formation and depositing an insulating layer in the recessed region. However, the process to recess the RMG may, among other issues, be unreliable and/or cause damage to the work-function metal. Therefore, a process for forming a SAC to a FET with a RMG that does not require recessing the RMG is desirable.